1. Field of the Invention
The present invention relates to the design of processors within computer systems. More specifically, the present invention relates to a method and an apparatus for speeding up program execution by storing results of resolvable branches during speculative execution and then using the results to predict the same branches during non-speculative execution.
2. Related Art
Advances in semiconductor fabrication technology have given rise to dramatic increases in microprocessor clock speeds. This increase in microprocessor clock speeds has not been matched by a corresponding increase in memory access speeds. Hence, the disparity between microprocessor clock speeds and memory access speeds continues to grow, and is beginning to create significant performance problems. Execution profiles for fast microprocessor systems show that a large fraction of execution time is spent not within the microprocessor core, but within memory structures outside of the microprocessor core. This means that the microprocessor systems spend a large fraction of time waiting for memory references to complete instead of performing computational operations.
Efficient caching schemes can help reduce the number of memory accesses that are performed. However, when a memory reference, such as a load operation generates a cache miss, the subsequent access to level-two (L2) cache or memory can require dozens or hundreds of clock cycles to complete, during which time the processor is typically idle, performing no useful work.
A number of techniques are presently used (or have been proposed) to hide this cache-miss latency. Some processors support out-of-order execution, in which instructions are kept in an issue queue, and are issued “out-of-order” when operands become available. Unfortunately, existing out-of-order designs have a hardware complexity that grows quadratically with the size of the issue queue. Practically speaking, this constraint limits the number of entries in the issue queue to one or two hundred, which is not sufficient to hide memory latencies as processors continue to get faster. Moreover, constraints on the number of physical registers, are available for register renaming purposes during out-of-order execution also limits the effective size of the issue queue.
Some processor designers have proposed a scout-ahead execution mode, wherein instructions are speculatively executed to prefetch future loads, but wherein results are not committed to the architectural state of the processor. For example, see U.S. patent application Ser. No. 10/741,944, filed Dec. 19, 2003, entitled, “Generating Prefetches by Speculatively Executing Code through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay. This solution to the latency problem eliminates the complexity of the issue queue and the rename unit, and also achieves memory-level parallelism.
However, since the results of the speculative execution are not committed to the architectural state of the processor, the code must be re-executed when the stall completes. This means that much of the work that was completed during the speculative execution must be repeated. In many cases this is wasteful. For example, the outcome branch operations can often be resolved during speculative execution. This information could be used to more-accurately predict branches during subsequent non-speculative execution, but this information is not saved in processor existing designs that support speculative execution.
Hence, what is needed is a method and an apparatus for saving the results of resolved branches during speculative execution to assist in predicting the same branches during non-speculative execution.